|
1.
(with
Mukherjee) “ An Evolutionary Algorithm for
VLSI Testing,”
5th International Mendel Conference
on Soft Computing, pp. 18 - 23, Brno, Czech
Republic, June 9 – 12, 1999
2.
(with
Mukherjee) “PLAGA:
A Highly Parallelizable Genetic Algorithm for
PLA Test Pattern Generation,” 1999 Congress
Evolutionary Computation,”
pp. 944-951, Washington DC, July 6 – 9,
1999.
3.
(with
Mukherjee) “Genetic Operators for Test Pattern
Generation in Programmable Logic Arrays,”
Recent Advances in Soft Computing 1999, pp.
158-165, De Montfort University at
U.K.
, July 1- 2, 1999.
4.
(with
R. Reilova) “A Hardware Performance Analysis
for a CAD Tool for PLA Testing,”
Midwest
Symposium
on Circuits and Systems 1997.
5.
“An
Object Oriented Programming Approach for the
Generation of Test Vectors for VLSI Design,”
ISCAS 1997.
6.
“A
New Approach in the Implementation of Test
Generation Algorithms for Programmable Logic
Arrays,” Proceedings of the 39th
Midwest
Symposium
on Circuits and Systems, August 1996.
7.
(with
R. Reilova) “Comparison of Two Leading
Algorithms for PLA Test Pattern Generation,”
Proceedings of the 39th
Midwest
Symposium
on Circuits and Systems, August 1996.
Extended
Publication List
A.
Referred
Articles (published or accepted).
1.
A
Hybrid Deterministic/Genetic Test Generator to
Improve Fault Effectiveness and Reduce CPU Time
Run", 2004 Congress Evolutionary Computation
(CEC), Portland, Oregon, June , 2004
2.
"Evolutionary
Algorithms for VLSITest Automation", ICCAD
paper number FLU604, for ICCAD 2003 has been
Approved for Review.
3.
(with
Mukherjee) “ An Evolutionary Algorithm for VLSI
Testing,” 5th International
Mendel Conference on Soft Computing,
Brno
,
Czech
Republic
,
June 9 –
12, 1999
4.
(with
Mukherjee) “PLAGA:
A Highly Parallelizable Genetic Algorithm for PLA
Test Pattern Generation,” 1999 Congress
Evolutionary Computation,”
Washington
DC
,
July 6 – 9, 1999
.
5.
(with
Mukherjee) “Genetic Operators for Test Pattern
Generation in Programmable Logic Arrays,” Recent
Advances in Soft Computing 1999,
De Montfort University at
U.K.
, July 1- 2,
1999, pp. 158-165.
6.
(with
R. Reilova) “A Hardware Performance Analysis for
a CAD Tool for PLA Testing,” Midwest Symposium
on Circuits and Systems 1997, approved for
publication and presentation.
7.
“An
Object Oriented Programming Approach for the
Generation of Test Vectors for VLSI Design,”
ISCAS 1997, accepted for publication.
8.
“A
New Approach in the Implementation of Test
Generation Algorithms for Programmable Logic
Arrays,” Proceedings of the 39th
Midwest
Symposium on
Circuits and Systems, August 1996.
9.
(with
R. Reilova) “Comparison of Two Leading
Algorithms for PLA Test Pattern Generation,”
Proceedings of the 39th
Midwest
Symposium on
Circuits and Systems, August 1996.
10.
“An
Ultra Fast Fault/Logic Simulator,” Proceedings
of the 38th
Midwest
Symposium on
Circuits and Systems, August 1995.
11.
“An
Improved Parallel Processing Fault Simulator
Algorithm: PLAto,” Proceedings of the Mardi
Grass High-Performance Computing Technologies
Conference,
Baton Rouge
,
LA
, February
1995.
12.
(with
D. Sarma) “Test Generation and Logic/Fault
Simulation of Programmable Logic Arrays: Optimized
Partitioning Techniques for Parallel
Processing,” Proceedings of the 37th Midwest
Symposium on Circuits and Systems, August, 1994,
Vol. ii, pp. 247-250.
13.
(with
D. Sarma) “PLAtano: A Parallel Processing Test
Vector Generator,” 37th
Midwest
Symposium on
Circuits and Systems, August 1994.
14.
(with
D. Sarma) “An Improved Fault Simulator: PLAto,”
Proc. of the 1992 International Conference on
Parallel Processing (ICCP’92), August 1992, Vol.
III, pp. 267-270.
15.
(with
D. Sarma) “A Novel Technique of PLA Test
Generation for Multiprocessing Environments,”
Proc. of the 24th
Midwest
Symposium on
Circuits and Systems, 1991, pp. 982-985.
16.
(with
D. Sarma) “Parallel Algorithm for PLA Test
Generation in CRAY YMP,” Proc. of Supercomputing
Symposium ’91, June 1991, pp. 365-374.
B.
International
Conferences and Invited Presentations.
1.
(with
Mukherjee) “ An Evolutionary Algorithm for VLSI
Testing,” 5th
International Mendel Conference on Soft
Computing,
Brno
,
Czech
Republic
,
June 9 –
12, 1999
.
2.
(with
Mukherjee) “PLAGA: A Highly Parallelizable
Genetic Algorithm for PLA Test Pattern
Generation,” 1999 Congress Evolutionary
Computation,”
Washington
DC
,
July 6 – 9, 1999
.
3.
(with
Mukherjee) “Genetic Operators for Test Pattern
Generation in Programmable Logic Arrays,” Recent
Advances in Soft Computing 1999, De Montfort
University at
U.K.
, July 1- 2,
1999.
4.
(with
R. Reilova) “A Hardware Performance Analysis for
a CAD Tool for PLA Testing,” Midwest Symposium
on Circuits and Systems 1997, approved for
presentation.
5.
“An
Object Oriented Programming Approach for the
Generation of Test Vectors for VLSI Design,”
ISCAS 1997, accepted for presentation.
6.
(with
R. Reilova) “An Exhaustive Hardware/Software
Analysis of Two VLSI Testing Tools,” ISCAS 1997,
accepted for poster presentation.
7.
“A
New Approach in the Implementation of Test
Generation Algorithms for Programmable Logic
Arrays,” Proceedings of the 39th
Midwest
Symposium on
Circuits and Systems, August 1996.
8.
(with
R. Reilova) “Comparison of Two Leading
Algorithms for PLA Test Pattern Generation,”
Proceedings of the 39th
Midwest
Symposium on
Circuits and Systems, August 1996.
9.
“An
Ultra Fast Fault/Logic Simulator,” Proceedings
of the 38th
Midwest
Symposium on
Circuits and Systems, August 1995.
10.
“An
Improved Parallel Processing Fault Simulator
Algorithm: PLAto,” Proceedings of the Mardi
Grass High-Performance Computing Technologies
Conference,
Baton Rouge
,
LA
, February,
1995.
11.
(with
D. Sarma) “Test Generation and Logic/Fault
Simulation of Programmable Logic Arrays: Optimized
Partitioning Techniques for Parallel
Processing,” Proceedings of the 37th
Midwest
Symposium on
Circuits and Systems, August 1994, Vol. II, pp.
247-250.
12.
(with
D. Sarma) “ PLAtano: A Parallel Processing Test
Vector Generator,” 37th
Midwest
Symposium on
Circuits and Systems, August 1994.
13.
(with
D. Sarma) “An Improved Fault Simulator: PLAto,”
Proc. of the 1992 International Conference on
Parallel Processing (ICCP’92), August 1992, Vol.
III, pp. 267-270.
14.
(with
D. Sarma) “A Novel Technique of PLA Test
Generation for Multiprocessing Environments,”
Proc. of the 24th
Midwest
Symposium on
Circuits and Systems, 1991, pp. 982-985.
15.
(with
D. Sarma) “Parallel Algorithm for PLA Test
Generation in CRAY YMP,” Proc. of Supercomputing
Symposium ‘91, June 1991, pp. 365-374.
C.
Student Conference Presentations.
1.
R.
Reilova (with Prof. Alfredo Cruz) “Comparison of
Two Leading Object Oriented Programming Algorithms
for PLA Test Pattern Generation,” 1997 Computing
Research Conference, Mayagüez,
Puerto Rico
, submitted
for presentation.
2.
R.
Reilova (with Prof. Alfredo Cruz) “Comparison of
Two Leading Algorithms for PLA Test Pattern
Generation,” 1997 Junior Technical Meeting.
3.
R.
Reilova (with Prof. Alfredo Cruz) “An Exhaustive
Hardware/Software Analysis of Two VLSI Testing
Tools,” 1997 Junior Technical Meeting.
4.
J.
A. Dastas (with Prof. A. Cruz) “Comparison of
the Implementation of Heapsort in AWK and C++,”
Computing Research Conference, April 1996, Mayagüez,
Puerto Rico
.
5.
E.
Jiménez, L. Maldonado and R. V. Valentín (with
Prof. A. Cruz) “Automatic Test Generation
Software to Detect Single Contact Faults in a
Programmable Logic Array,” Computing Research
Conference, April 1996, Mayagüez,
Puerto Rico
.
6.
J.
Ortega (with Prof. A. Cruz) “Comparison of the
Performance of the Binary Search Algorithm in AWK
and C Language,” Computing Research Conference,
April 1996, Mayagüez,
Puerto Rico
.
7.
R.
V. Valentín (with Prof. A. Cruz) “Shell Sort
Implementation and Comparison Using C Language and
AWK Under UNIX Operating System,” Computing
Research Conference, April 1996, Mayagüez,
Puerto Rico
.
8.
R.
Reilova and S. Vilá (with Prof. A. Cruz) “UNIX
Curses Text Editor Software to Aid in Computer
Program Development and General Text Applications
on Text-Based Terminals,” Computing Research
Conference, April 1996, Mayagüez, Puerto Rico.
9.
J.
A. Dastas (with Prof. A. Cruz) “Comparison of
the Implementation of Heapsort in AWK and C++,”
XI Seminario Interuniversitario de Investigación
Matemática y Ciencias de Cómputos, April 1996,
Arecibo
,
Puerto Rico
.
10.
R.
Reilova (with
Prof. A. Cruz) “UNIX Curses Text Editor Software
to Aid in Computer Program Development and General
Text Applications on Text-Based Terminals,” XI
Seminario Interuniversitario de Investigación
Matemática y Ciencias de Cómputos, April 1996,
Arecibo, Puerto Rico.
11.
J.
A. Dastas (with Prof. A. Cruz) “Comparison of
the Implementation of Heapsort in AWK and C++,”
ACS Junior Technical Meeting, March 1996,
Arecibo
,
Puerto Rico
.
12.
R.
V. Valentín (with Prof. A. Cruz) “Automatic
Test Generation Software to Detect Single Contact
Faults in a Programmable Logic Array,” ACS
Junior Technical Meeting, March 1996,
Arecibo
,
Puerto Rico
.
13.
C.
De La Torre (with Prof. A. Cruz) “A Digital Test
for PLA’s Using Classical and Matrix Methods,”
ACS Junior Technical Meeting, March 1996, Arecibo,
Puerto Rico.
14.
J.
Gómez (with Prof. A. Cruz) “An Artificial
Intelligence Program for Chess Endgames,”
Computing Research Conference, April 1995, Mayagüez,
Puerto Rico
.
15.
S.
Vilá and D. Mercado (with Prof. A. Cruz)
“Comparison of the Implementation of Quicksort
in AWK and Pascal,” Computing Research
Conference, April 1995, Mayagüez,
Puerto Rico
.
D.
Student Publications.
1.
R.
Reilova (with Prof. Alfredo Cruz) “Comparison of
Two Leading Object Oriented Programming Algorithms
for PLA Test Pattern Generation,” 1997 Computing
Research Conference, Mayagüez,
Puerto Rico
, submitted
for publication.
2.
R.
Reilova (with Prof. Alfredo Cruz) “Comparison of
Two Leading Algorithms for PLA Test Pattern
Generation,” 1997 Junior Technical Meeting.
3.
R.
Reilova (with Prof. Alfredo Cruz) “An Exhaustive
Hardware/Software Analysis of Two VLSI Testing
Tools,” 1997 Junior Technical Meeting.
4.
J.
A. Dastas (with Prof. A. Cruz) “Comparison of
the Implementation of Heapsort in AWK and C++,”
Computing Research Conference, April 1996, Mayagüez,
Puerto Rico
.
5.
E.
Jiménez, L. Maldonado and R. V. Valentín (with
Prof. A. Cruz) “Automatic Test Generation
Software to Detect Single Contact Faults in a
Programmable Logic Array,” Computing Research
Conference, April 1996, Mayagüez,
Puerto Rico
.
6.
J.
Ortega (with Prof. A. Cruz) “Comparison of the
Performance of the Binary Search Algorithm in AWK
and C Language,” Computing Research Conference,
April 1996, Mayagüez,
Puerto Rico
.
7.
R.
V. Valentín (with Prof. A. Cruz) “Shell Sort
Implementation and Comparison Using C Language and
AWK Under UNIX Operating System,” Computing
Research Conference, April 1996, Mayagüez,
Puerto Rico
.
8.
R.
Reilova and
S. Vilá (with Prof. A. Cruz) “UNIX Curses Text
Editor Software to Aid in Computer Program
Development and General Text Applications on
Text-Based Terminals,” Computing Research
Conference, April 1996, Mayagüez, Puerto Rico.
9.
J.
A. Dastas (with Prof. A. Cruz) “Comparison of
the Implementation of Heapsort in AWK and C++,”
Seminario Interuniversitario de Investigación
Matemática y Ciencias de Cómputos, April 1996,
Arecibo
,
Puerto Rico
.
10.
R.
Reilova and S. Vilá (with Prof. A. Cruz) “UNIX
Curses Text Editor Software to Aid in Computer
Program Development and General Text Applications
on Text-Based Terminals,” Seminario
Interuniversitario de Investigación Matemática y
Ciencias de Cómputos, April 1996, Arecibo, Puerto
Rico.
11.
J.
A. Dastas (with Prof. A. Cruz) “Comparison of
the Implementation of Heapsort in AWK and C++,”
ACS Junior Technical Meeting, March 1996,
Arecibo
,
Puerto Rico
.
12.
R.
V. Valentín (with Prof. A. Cruz) “Automatic
Test Generation Software to Detect Single Contact
Faults in a Programmable Logic Array,” ACS
Junior Technical Meeting, March 1996,
Arecibo
,
Puerto Rico
.
13.
C.
De La Torre (with Prof. A. Cruz) “A Digital Test
for PLA’s Using Classical and Matrix Methods,”
ACS Junior Technical Meeting, March 1996, Arecibo,
Puerto Rico.
14.
J.
Gómez (with Prof. A. Cruz) “An Artificial
Intelligence Program for Chess Endgames,”
Computing Research Conference, April 1995, Mayagüez,
Puerto Rico
.
15.
S.
Vilá and D. Mercado (with Prof. A. Cruz)
“Comparison of the Implementation of Quicksort
in AWK and Pascal,” Computing Research
Conference, April 1995, Mayagüez,
Puerto Rico
.
E.
Additional Selected Presentations.
1.
“A
Parallel Processing Algorithm for a Classical
Default Simulator,” Technical Report # TR
134/92ECE,
University
of
Cincinnati
, January
1992.
2.
“Test
Generation and Logic/Fault Simulation of
Programmable Logic Arrays: Optimized Partitioning
for Parallel Processing,” PhD thesis,
University
of Cincinnati
,
OH
, January
1992.
|
