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	   ///
	  ///  to add a Page:
     ///   U can copy the following commented line, uncomment it and enter the text
    ///    Page["TitleOfYourPage"] = "Text of The Page.";
   ///     JSCMS v1.03
  ///      Copyright SIX ORANGES ;  info@ci3.net
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var Page = new Object;

// here u have to put NEWS in order to appear first in the list
Page["Home"] = "<h3> <font color=gray> [ADSD-RHL]-ADVANCED DIGITAL DESIGN-RECONFIGURABLE HARDWARE LABORATORY</font></h3><b> Welcome to the Reconfigurable Hardware Laboratory Web Page</b><br> The Reconfigurable Hardware Laboratory is an installation where the logic design is taken to a higher level of complexity for PUPR students and professors. Using the FPGA technology, this laboratory is intended as a support facility for the areas of Logic Circuits, Computer Architecture, Digital Signal Processing, Data Communication, and Automatic Controls. In this lab, graduate and undergraduate students can implement their designs and see them working in record time without the limitations of discrete components.<br><br>  The ADSD-RHL was created using a donation from <a href=\"http://www.xilinx.com\"> Xilinx</a>, who kindly provided the software and hardware currently being used in the courses of Computer Architecture and Undergraduate Research. <br> <br> The main objective of the laboratory is provide a tool for fast implementation of custom designed digital circuits using the intelectual property provided by <a href=\"http://www.xilinx.com\"> Xilinx</a>, either using their <a href=\"http://www.xilinx.com/ise/optional_prod/system_generator.htm\"> System Generator</a>, or their design tool <a href=\"http://www.xilinx.com/ise/logic_design_prod/foundation.htm\">ISE</a>"; Page["People"] = "<h3><font color=gray>Laboratory Staff</font></h3><br><b> <a  href=\"http://www.pupr.edu/mteixeir/faculty_page/A_Gonzalez_Page.htm\"> Angel Gonzalez Lizardo, PhD. </a></b> <br> Associate Professor <br> <br><b><a  href=\"http://www.pupr.edu/mteixeir/faculty_page/O_Rodriguez_Page.htm\">  Othoniel Rodriguez, PhD.</a></b><br> Associate Professor <br><br> <b> Michael Gonzalez Feliciano</b> <br> Undergraduate Student";
Page["Lab Projects"] = "<h3> <font color=gray> PROJECTS </font></h3> </font> <h4> RAY-PROJECTION CO-PROCESSOR </h4> A floating-point coprocessor to perform repetitive calculations in a ray-projection algorithm developed by professor <a href=\"http://www.pupr.edu/mteixeir/faculty_page/F_Nevarez_Page.htm\">Felix Nevarez </a> is under design as the Capstone Project of the student Michael Gonzalez. <h4> New Graduate Course: <I>  VHDL Fundamentals for DSP, Controls, and Communications </I>  </h4> </b> This course was taught as a special topic to provide graduate students with basic knowledge about digital circuits design modern techniques. The platform used was Xilinx ISE Foundation and System Generator, along with Matlab and Simulink. <br>   <br>  <a href= \"index_docs/syllabus.pdf\"> Syllabus </a> <br><br>   <a href= \"index_docs/VHDL_FUNDAMENTALS_1.pdf\"> Presentations </a>(...to be continued)  <br> <h4> Projects.</h4> <a href=\"VHDL_FUND_FA05/VHDL_Fund_Project_James_Acosta.htm\"> Adaptive Power Filter by James Acosta. </a> <br> <a href=\"VHDL_FUND_FA05/Two_dimensional_position_control.htm\"> XY positioning system by Wence Lopez and Cesar Cabrera </a> <br> Circular Convolution Device by Ivan Rodriguez <br> Smart Antenna processor by Angel Sepulveda <br> <br> <h4>Smart Antenna Algorithm</h4> Evaluation of the requirements for the implementation of a smart antenna beamforming algorithm developed by <a href=\"http://www.pupr.edu/mteixeir/faculty_page/V_Zaharov_Page.htm\"> Dr. Victor Zaharov</a>, and implementation of a working prototype on a programmable logic device.<br> <br> <a href= \"index_docs/Papers_presentation.htm\"> <h4> Literature Review on Reconfigurable Hardware. </h4>  </a>As part of an ongoing undergraduate research program, the student Michael Gonzalez produced a collection of documents related to programmable logic. Some of them are displayed here."; 
Page["Pictures"]="<center> <h3> <font color=gray> UNDERGRAD STUDENTS WORKING AT THE LAB</font> </h3><b><br> <img src=\"images/DSC02353.JPG\" width=512  height=342> <img src=\"images/DSC02354.JPG\" width=512  height=342> <br> Students working on their lab projects </center> "; 
Page["Publications"]="<h2> <font color=gray> Publications Related to The Laboratory.</h2> </font> <ol> <li> <b> FPGA Based Control Scheme For Active Power Filter.</b> James Acosta and Angel González. accepted for publication at the <a href=\"http://www.ieee.org.ve/eventos/td2006/index.htm\"><i> IEEE Transmission and Distribution Conference and Exposition </i></a> in Caracas, Venezuela on August 15 to 18, 2006.   </li> <li> <b> FPGA Based Control Scheme For Active Power Filter.</b> James Acosta and Angel González.  <i> 41st ACS Junior Technical Meeting 26th Puerto Rico Interdisciplinary Scientific Meeting (PRISM).</i> University of Puerto Rico, Cayey Campus. March 11, 2006  </li> <li> <b> FPGA Based Control Scheme For Active Power Filter.</b> James Acosta and Angel González. Accepted for publication at <i> IEEE Transmission and Distribution Conference and Exposition</i>, February, 2006. </li> <li> <b> Active Power Filter Control Implemented using VHDL. </b> James Acosta and Angel Gonzalez. Poster Section. <i> PUPR Student Research Exhibition.</i> San Juan, Puerto Rico.  ";