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Research
in GaAs and Si CMOS devices, digital logic
design and testing.
(5-94-8/01)
Development of accurate physically based
analytical bulk CMOS inversion and
accumulation short-channel device models
for ultra-small low-power devices to be
used in Giga- and Tera- scale Integration.
Generalized threshold voltage
roll-off and subthreshold slope roll-up
models applicable to all bulk CMOS
structures were obtained.
(
6/92-5/94) Characterized GaAs logic
structures using HSPICE simulations. A new
low power/reduced area GaAs dynamic logic
style was developed.
(4/89-6/92)
Designed, fabricated and tested optically
programmable
CMOS logic arrays for real-time
microprocessor reconfigurability. This
work entailed device modeling, logic
design, SPICE simulations, chip layout and
fabrication through a foundry and
functional/parametric testing of the
fabricated chips.
(1/89-3/89)
Developed a VLSI sub-system for a
1024-processor parallel machine using the
Genesis Silicon compiler.
Related
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